The present invention relates generally to electronic circuits, and more particularly, to electronic circuit memory testing and repair.
Electronic circuits such as microprocessors, microcontrollers (MCUs), systems-on-chips (SOCs), and application specific integrated circuits (ASICs) are widely used in various applications including industrial applications, automobiles, home appliances, and handheld devices. These electronic circuits include multiple circuit modules such as hard and soft IP cores, digital logic gates, flip-flops, and latches. A circuit module often includes one or more memory blocks for storing data. Memory locations within the memory blocks are required to function properly when a read/write operation is performed. However, due to various factors including process, voltage and temperature (PVT) variations, and overheating of the electronic circuit, some memory locations may be damaged.
A memory testing mechanism, typically referred to as a built-in-self-test (BIST) engine, is provided in an electronic circuit to test memory locations within a memory block and generate memory test data. Additionally, each memory block has a corresponding repair register that stores the memory test data, i.e., the memory repair data, generated by the corresponding BIST engine. The BIST engine transmits memory repair data to a fuse processor that permanently burns the repair data to a fuse storage device in the electronic device. When the electronic circuit is switched on, the fuse processor fetches the memory repair data from the fuse storage device and provides it to a corresponding BIST engine. The BIST engines use the memory repair data to prevent a faulty memory location from being used during a memory read/write operation.
Since electronic circuits may include multiple circuit modules that operate at different frequencies, handshaking logic is used to synchronize the frequencies during a memory repair operation.
FIG. 1 shows a schematic block diagram of an exemplary conventional electronic circuit 100. The electronic circuit 100 includes first through third circuit modules 102a-102c (collectively referred to as circuit modules 102), handshake logic 104, fuse processor 106, and fuse storage device 108. The first through third circuit modules 102a-102c include corresponding first through third memory blocks 110a-110c (collectively referred to as memory blocks 110), corresponding first through third BIST engines 112a-112c (collectively referred to as BIST engines 112), and corresponding first through third repair registers 114a-114c (collectively referred to as repair registers 114), respectively. The fuse processor 106 includes a programmable data register 116.
An output terminal of the third repair register 114c is connected to an input terminal of the second repair register 114b and an output terminal of the second repair register 114b is connected to an input terminal of the first repair register 114a, by way of the handshaking logic 104. An output terminal of the first repair register 114a is connected to an input terminal of the programmable data register 116. An output terminal of the programmable data register 116 is connected to the fuse storage device 108. The first circuit module 102a may include a processor core, such as a digital signal processor (DSP) or a power processor core. The second and third circuit modules 102b and 102c may include digital circuits, such as flip-flops, logic gates, latches, and combinations thereof.
An external testing apparatus (not shown) is connected to the electronic circuit 100 to initiate the BIST engines 112 and test the corresponding memory blocks 110. The external testing apparatus may be connected to a suitable test interface, such as a joint test action group (JTAG) interface of the electronic circuit 100, which is further connected to each BIST engine 112. The BIST engines 112 generate different test patterns for testing the corresponding memory blocks 110.
The first circuit module 102a operates at a first clock frequency and the second and third circuit modules 102b and 102c operate at a second clock frequency. The external testing apparatus configures the first circuit module 102a and initiates a memory repair operation on the first memory block 110a by initiating the first BIST engine 112a. The first BIST engine 112a tests the first memory block 110a and generates first memory repair data that is stored in the first repair register 114a. Since the operating frequency (first clock frequency) of the first circuit module 102a is different from the operating frequencies (second clock frequency) of the second and third circuit modules 102b and 102c, the first memory repair data is transferred to the fuse processor 106 during a first test cycle by way of the handshake logic 104. The handshake logic 104 operates at the second clock frequency and synchronizes the first memory repair data with the second clock frequency. The programmable data register 116 receives and transfers the first memory repair data to the fuse storage device 108.
Thereafter, the external testing apparatus configures the second and third circuit modules 102b and 102c and initiates corresponding second and third BIST engines 112b and 112c, which in turn launch memory repair operations on the second and third memory blocks 110b and 110c respectively, in a second test cycle. The second and third memory blocks 110b and 110c generate second and third memory repair data that are stored in the second and third repair registers 114b and 114c, respectively. The second and third circuit modules 102b and 102c transfer the second and third memory repair data to the fuse processor 106, during the second test cycle, by way of the handshake logic 104. The handshake logic 104 synchronizes with the first clock frequency when the second and third memory repair data enters the first repair register 114a and with the second clock frequency when the second and third memory repair data exit the first repair register 114a. The programmable data register 116 receives and transfers the first memory repair data to the fuse storage device 108, which permanently stores the second and third memory repair data. Thus, the first and second memory repair data are independently and separately transmitted to the fuse processor 106, which increases overall memory test and repair time considerably.
Therefore, it would be advantageous to reduce memory test and repair time, and eliminate the above-mentioned shortcomings of conventional electronic circuits.